In modern Direct Sequence Spread Spectrum (DSSS) communication systems, the Walsh coding schemes used may vary from one operational mode to another and from one network to another. In addition, certain communication devices may be required to operate across multiple networks that have adopted different Walsh coding standards (i.e., multi-mode operation).
As it is desirable to build receivers that may operate in a multitude of different modes and within multiple networks and systems, a flexible and modular method and apparatus for Walsh code generation is desired that will accommodate these schemes in an efficient manner (e.g., having significant sharing of hardware and software resources between the various modes of operation and between different systems). In particular, the ability to efficiently generate Walsh sequences in certain communication systems is desirable.
It is also desirable to provide a flexible and efficient interface to the sequence generator so that the number of sequence bits provided per access can be varied to match the requirements of the requester. Thereby reducing the number of requests per time interval.
DSSS receivers have traditionally been capable of demodulation in only a single or perhaps a few modes of operation and do not typically have the flexibility to accommodate the variety of spreading, modulation and coding schemes supported by the current invention. For example, mobile station receivers compliant with the TIA/EIA-IS-95-B standard are required to generate only 64-bit Walsh codes.
Walsh code bit sequences are traditionally generated by replicating a pattern of inverted and non-inverted versions of the next smaller Walsh code as described in the literature. The pattern of such inverted/non-inverted sequences is such that if column and row indexes are applied (in binary format) to each bit in the Walsh matrix, the inverted portion of the larger Walsh matrix is the bits with index values containing a “1” in the most significant bit (MSB) of both the row and the column index numbers. As this concept is extended to longer and longer Walsh codes, the inversion process causes some sections to be repeatedly inverted, so every other time they are inverted the original bit pattern once again appears due to the double inversion. So an algorithm can be applied to this process to determine whether a particular section of a longer Walsh code has been inverted relative to the same section of a shorter Walsh code. Using a Walsh symbol index (row index W) and a specific bit location (column index B) within that particular Walsh symbol, delete the lower order row and column bits up to the number of bits required to index rows and columns in the smaller Walsh table. Therefore, if the longer table is twice the size of the smaller table, only one index bit would remain for the row and column indexes, if the longer table is 4 times the size of the smaller two bits would remain, and so on. With the remaining bits fields, logically AND the row and column indexes together, then count the number of 1's in the result. If that number is odd, the field was inverted (odd number of inversions=inverted), if it is even, the field was not inverted (even number of inversions=not inverted). The counting of the number of 1's can be easily accomplished in logic using Exclusive-OR logic gates.
A need exists in the art for a method and apparatus that can be easily adapted to any random length Walsh code sequence and any random number of bits provided per access. It should also preferably provide the additional benefit of being capable of producing a new access on every clock cycle, thus maximizing the efficiency of the bit sequence requesting process.